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In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays.
YaJuan Hui
Qingzhen Li
Leimin Wang
Cheng Liu
Deming Zhang
Xiangshui Miao
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2024)
Keyphrases
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random access memory
low voltage
tree structure
design considerations
power system
index structure
binary tree
main memory
memory usage
high voltage
tree models
power supply
r tree
linear space
hash table
electric field
tree nodes
limited memory
tree structures