A low power based system partitioning and binding technique for multi-chip module architectures.
Raghava V. CherabuddiMagdy A. BayoumiH. KrishnamurthyPublished in: Great Lakes Symposium on VLSI (1997)
Keyphrases
- low power
- ultra low power
- high speed
- low cost
- single chip
- mixed signal
- power consumption
- cmos technology
- low power consumption
- signal processor
- power dissipation
- image sensor
- wireless transmission
- high power
- vlsi circuits
- digital signal processing
- nm technology
- real time
- logic circuits
- vlsi architecture
- energy efficiency
- image processing
- cmos image sensor