A VLSI architecture for hierarchical mesh based motion compensation using scalable affine transformation core.
Wael M. BadawyGuoqing ZhangMichael TalleyMagdy A. BayoumiPublished in: ISCAS (2000)
Keyphrases
- motion compensation
- affine transformation
- vlsi architecture
- motion estimation
- low complexity
- motion compensated
- video compression
- motion vectors
- video coding
- low power
- vlsi implementation
- image registration
- image matching
- motion field
- feature points
- b spline
- real time
- high speed
- video sequences
- computational complexity
- inter frame
- video codec
- power consumption
- image coding
- video data