Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs.
Olujide A. AdeniranAndreas DemosthenousPublished in: ECCTD (2005)
Keyphrases
- low power
- cmos technology
- low voltage
- random access memory
- power consumption
- high speed
- low cost
- mixed signal
- power management
- single chip
- vlsi circuits
- image sensor
- logic circuits
- power dissipation
- digital signal processing
- design considerations
- parallel processing
- low power consumption
- power reduction
- nm technology
- gate array
- real time
- analog to digital converter