Efficient and Scalable Architecture for Multiple-Chip Implementation of Simulated Bifurcation Machines.
Tomoya KashimataMasaya YamasakiRyo HidakaKosuke TatsumuraPublished in: IEEE Access (2024)
Keyphrases
- vlsi implementation
- highly optimized
- layered architecture
- efficient implementation
- high speed
- lightweight
- architectural design
- low cost
- instruction set
- software architecture
- memory management
- highly efficient
- hardware implementation
- management system
- design considerations
- circuit design
- floating point
- client server architecture
- modular design
- functional units
- reconfigurable hardware
- analog vlsi