Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization.
Hisaaki KatagiriKeiichi YasumotoAkira KitajimaTeruo HigashinoKenichi TaniguchiPublished in: DAC (2000)
Keyphrases
- hardware implementation
- communication protocols
- concurrent programs
- process algebra
- signal processing
- efficient implementation
- software implementation
- fpga implementation
- communication networks
- communication protocol
- image processing algorithms
- dedicated hardware
- hardware design
- field programmable gate array
- hardware architecture
- pipeline architecture
- pipelined architecture
- memory management
- image binarization
- protocol specification
- general purpose processors
- machine learning
- neural network
- parallel architecture
- fpga device
- information systems
- computer vision