Model Checking for an HDLC IP Core Transparency Error in an Aerospace Industrial Context.
Shiyu LiuDongfang LiJixing XueGuang YangWei ShenZhihao WangPublished in: CSSE (2021)
Keyphrases
- model checking
- temporal logic
- formal methods
- model checker
- symbolic model checking
- formal verification
- partial order reduction
- temporal properties
- automated verification
- finite state machines
- finite state
- reachability analysis
- verification method
- bounded model checking
- formal specification
- concurrent systems
- transition systems
- pspace complete
- timed automata
- computation tree logic
- epistemic logic
- reactive systems
- process algebra
- symbolic representation
- modal logic
- deterministic finite automaton
- linear time temporal logic
- binary decision diagrams