A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET.
Yohan FransMohamed ElzeftawiHiva HedayatiJay ImVassili KireevToan PhamJaewook ShinParag UpadhyayaLei ZhouSantiago AsuncionChris BorrelliGeoff ZhangHongtao ZhangKen ChangPublished in: VLSI Circuits (2016)