Low power and high performance clock delayed domino logic using saturated keeper.
Amir AmirabadiA. ChehelcheraghiS. H. RasouliA. SeyediAli Afzali-KushaPublished in: ISCAS (2006)
Keyphrases
- low power
- power consumption
- high speed
- logic circuits
- low power consumption
- signal processor
- delay insensitive
- low cost
- single chip
- high power
- vlsi architecture
- power saving
- wireless transmission
- digital signal processing
- power reduction
- mixed signal
- power dissipation
- image sensor
- vlsi circuits
- wide dynamic range
- gate array
- asynchronous circuits
- image processing