Aspects Regarding the Implementation of Hsiao Code to the Cache Level of a Memory Hierarchy with Fpga Xilinx Circuits.
Ovidiu-Constantin NovacSt. Vari-KakasF. I. HathaziMircea CurilaSorin CurilaPublished in: SCSS (2) (2008)
Keyphrases
- memory hierarchy
- hardware implementation
- hardware description language
- memory management
- high speed
- hardware architecture
- field programmable gate array
- fpga implementation
- computing power
- computer architecture
- fpga device
- hardware design
- dedicated hardware
- integrated circuit
- main memory
- control flow
- memory access
- secondary storage
- efficient implementation
- signal processing
- real time
- pipelined architecture
- image processing algorithms
- source code
- low cost
- response time
- query processing