A hardware acceleration scheme for memory-efficient flow processing.
Xin YangSakir SezerShane O'NeillPublished in: SoCC (2014)
Keyphrases
- memory efficient
- real time
- parallel architecture
- data processing
- processing capabilities
- data acquisition
- protection scheme
- vlsi implementation
- multithreading
- low cost
- hardware and software
- iterative deepening
- multiple sequence alignment
- external memory
- central processor
- low latency
- processing units
- computational power
- hardware implementation
- flow field
- computer systems
- massively parallel
- embedded systems
- flow patterns
- index structure