A Resource-Saving Energy-Efficient Reconfigurable Hardware Accelerator for BERT-based Deep Neural Network Language Models using FFT Multiplication.
Rodrigue RizkDominick RizkFrederic RizkAshok KumarMagdy A. BayoumiPublished in: ISCAS (2022)
Keyphrases
- language model
- energy efficient
- neural network
- reconfigurable hardware
- field programmable gate array
- floating point
- wireless sensor networks
- energy consumption
- sensor networks
- low cost
- information retrieval
- probabilistic model
- hardware software
- hardware implementation
- energy efficiency
- routing protocol
- base station
- data transmission
- image processing
- processing elements
- parallel implementation
- pattern recognition
- associative memory
- functional units
- embedded systems
- parallel computing
- routing algorithm
- resource management
- hardware architecture
- sensor nodes
- shortest path
- machine learning