Resource efficient implementation of a 10Gb/s radio receiver baseband in FPGA.
Christer SvenssonZhongxia Simon HeHerbert ZirathLei BaoJingjing ChenPublished in: FPGAworld (2013)
Keyphrases
- efficient implementation
- hardware implementation
- high speed
- field programmable gate array
- physical layer
- hardware design
- active set
- hardware architecture
- real time
- efficient processing
- software defined radio
- resource management
- fpga implementation
- resource allocation
- real time image processing
- highly parallel
- image processing algorithms
- wireless communication
- fading channels
- computing systems
- parallel algorithm
- data acquisition
- low cost
- face recognition