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As FinFET with gate-to-source/drain underlap for sub-14 nm technology node to impede short channel effect.

Jay PathakAnand D. Darji
Published in: IET Circuits Devices Syst. (2019)
Keyphrases
  • nm technology
  • power consumption
  • low power
  • multi channel
  • multiple input
  • field effect transistors
  • power dissipation
  • tree structure
  • destination node
  • real time
  • neural network
  • image segmentation
  • directed graph