Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra.
Anchit ArunAnanya ChakrabortyPriyanka DuttaDebajyoti PalTridibesh NagDebasis DeSudip GhoshHafizur RahamanPublished in: IAIT (2023)
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