Design and Implementation of a Prioritized Packet-Processing Module on NetFPGA Platform.
Pang-Wei TsaiHou-Yi ChouPei-Wen ChengMon-Yen LuoChu-Sing YangPublished in: HPCC/EUC (2013)
Keyphrases
- reconfigurable hardware
- design considerations
- real time
- low cost
- pilot testing
- implementation issues
- design methodology
- verilog hdl
- circuit design
- distributed architecture
- data processing
- case study
- efficient implementation
- data acquisition
- architectural design
- core components
- parallel architecture
- information processing