Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture.
Zahid KhanTughrul ArslanPublished in: DATE (2007)
Keyphrases
- vlsi architecture
- real time
- low density parity check
- low cost
- low complexity
- low power
- general purpose processors
- hardware implementation
- vlsi implementation
- instruction set
- parallel architecture
- instruction set architecture
- distributed video coding
- ldpc codes
- rate distortion
- motion estimation
- decoding algorithm
- turbo codes
- non binary
- embedded systems
- motion vectors
- video data