Model Checking Weighted Integer Reset Timed Automata.
Lakshmi ManasaShankara Narayanan KrishnaChinmay JainPublished in: Theory Comput. Syst. (2011)
Keyphrases
- timed automata
- model checking
- temporal logic
- reachability analysis
- formal verification
- finite state
- partial order reduction
- symbolic model checking
- model checker
- temporal properties
- formal specification
- automated verification
- pspace complete
- verification method
- finite state machines
- bounded model checking
- formal methods
- transition systems
- theorem prover
- concurrent systems
- computation tree logic
- epistemic logic
- planning domains
- first order logic
- bayesian networks
- process algebra
- deterministic finite automaton
- software development