ASIC and FPGA implementations of H.264 DCT and quantization blocks.
Roman C. KordasiewiczShahram ShiraniPublished in: ICIP (3) (2005)
Keyphrases
- hardware implementation
- dct coefficients
- hardware architecture
- software implementation
- single chip
- hardware architectures
- discrete cosine transform
- discrete cosine transformation
- efficient implementation
- block size
- xilinx virtex
- image blocks
- field programmable gate array
- adaptive quantization
- transform domain
- transform coefficients
- dct domain
- general purpose processors
- spatial domain
- signal processing
- jpeg compressed images
- image compression
- low power
- jpeg compression
- application specific integrated circuits
- watermarking algorithm
- low bit rate
- compressed domain
- blocking artifacts
- jpeg images
- design methodology
- low cost
- high speed
- frequency domain
- digital images
- compressed images
- quadtree
- integrated circuit
- fpga device
- circuit design
- image coding
- block coding
- continuous tone images
- coded images
- watermark embedding