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A 0.8-mW 5-bit 250-MS/s Time-Interleaved Asynchronous Digital Slope ADC.
Pieter Harpe
Cui Zhou
Kathleen Philips
Harmke de Groot
Published in:
IEEE J. Solid State Circuits (2011)
Keyphrases
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analog to digital converter
digital straight line
power consumption
digital images
digital content
shift register
sigma delta
learning algorithm
constraint satisfaction problems
circuit design
power supply
asynchronous communication