Low-power partial-parallel Chien search architecture with polynomial degree reduction.
Xinmiao ZhangItai DrorSanel AltermanPublished in: ISCAS (2016)
Keyphrases
- low power
- power consumption
- vlsi architecture
- low cost
- high speed
- power reduction
- vlsi circuits
- cmos technology
- high power
- nm technology
- mixed signal
- single chip
- digital signal processing
- hardware and software
- parallel processing
- real time
- low power consumption
- design considerations
- image sensor
- shared memory
- data flow