Low Power Flip-Flop Design Using Tri-State Inverter Logic.

P. Indira M. Kamaraju

Published in: J. Low Power Electron. (2019)

Keyphrases

low power
logic circuits
power dissipation
cmos technology
power consumption
single chip
low cost
flip flops
low power consumption
high speed
digital signal processing
vlsi architecture
gate array
mixed signal
design process
computer vision
ultra low power
circuit design
power reduction
delay insensitive
vlsi circuits