Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit.
Premysl SuchaZdenek PohlZdenek HanzálekPublished in: IEEE Real-Time and Embedded Technology and Applications Symposium (2004)
Keyphrases
- iterative algorithms
- scheduling algorithm
- pipelined architecture
- hardware implementation
- low cost
- high speed
- scheduling problem
- dual formulation
- parallel architecture
- real time
- field programmable gate array
- single chip
- resource allocation
- flexible manufacturing systems
- real time image processing
- signal processing
- hardware architecture
- iterative methods
- low rank approximation
- fpga implementation
- response time
- data flow
- hardware design
- round robin
- arithmetic operations
- linear array