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Design of an ultra-low power, low complexity and low jitter PLL with digitally controlled oscillator.
N. K. Anushkannan
H. Mangalam
Published in:
Int. J. Adv. Intell. Paradigms (2020)
Keyphrases
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low complexity
vlsi architecture
wireless video
computational complexity
motion estimation
low power
lower complexity
ultra low power
real time
machine learning
response time
low cost
bit plane
multiple description coding
mode decision
low density parity check