A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications.
Avanindra MadisettiAlan N. Willson Jr.Published in: IEEE Trans. Circuits Syst. Video Technol. (1995)
Keyphrases
- discrete cosine transform
- high speed
- low power
- image compression
- clock frequency
- transform domain
- single chip
- power consumption
- dct coefficients
- high definition
- filter bank
- high frequency
- fpga device
- dct domain
- real time
- cmos technology
- xilinx virtex
- video conferencing
- spatial domain
- general purpose
- computer vision
- parallel architecture
- subband
- video encoder
- multiresolution