Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata.
Remy ChevallierEmmanuelle Encrenaz-TiphèneLaurent FribourgWeiwen XuPublished in: FORMATS (2006)
Keyphrases
- timed automata
- model checking
- temporal logic
- reachability analysis
- formal verification
- high speed
- memory management
- main memory
- memory usage
- real time systems
- software architecture
- management system
- associative memory
- first order logic
- asynchronous circuits
- analog vlsi
- theorem prover
- data flow
- knowledge base
- hardware design
- multithreading
- verification method
- memory hierarchy
- electronic circuits
- operating system