REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs.
Abbas BanaiyanMofradHouam HomayounVasileios KontorinisDean M. TullsenNikil D. DuttPublished in: IGCC (2013)
Keyphrases
- fault tolerant
- low power
- vlsi architecture
- power consumption
- fault tolerance
- low cost
- high speed
- cmos technology
- distributed systems
- mixed signal
- nm technology
- single chip
- load balancing
- signal processor
- logic circuits
- real time
- low power consumption
- power reduction
- image sensor
- vlsi circuits
- gate array
- ultra low power
- digital signal processing