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A high performant 0.5 μm CMOS single chip ISDN network termination based on an embedded core and co-processor architecture.
P. Wouters
P. Van Oostende
L. Dawance
B. Graindourze
Published in:
ICECS (1998)
Keyphrases
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single chip
embedded processors
cmos image sensor
software implementation
low power
low cost
highly parallel
low power consumption
image sensor
high speed
signal processor
cmos technology
power consumption
embedded systems
real time
image processing algorithms