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VLIW-aware software optimization of AAC decoder on parallel architecture core DSP (PACDSP) processor.
Tsung-Han Tsai
Chun-Nan Liu
Jui Hong Hung
Published in:
IEEE Trans. Consumer Electron. (2008)
Keyphrases
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parallel architecture
systolic array
data flow
parallel processing
hardware implementation
shared memory
distributed memory
high level synthesis
computer systems
signal processing
processing elements
parallel implementation
synthetic aperture sonar
high speed
embedded systems
dynamic programming
np hard