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Evaluation of 8b/10b FPGA Encoder Implementations for SerDes Links.
Andrés Quesada-Martínez
Javier Aparicio-Morales
José Campos-Araya
Alfonso Chacón-Rodríguez
Ronny García-Ramírez
Renato Rimolo-Donadio
Published in:
LASCAS (2020)
Keyphrases
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high speed
software implementation
evaluation model
low complexity
efficient implementation
video codec
real time image processing
hardware architectures
data sets
low cost
bit rate
rate distortion
evaluation method
hardware implementation