A 0.4 V 180 nm CMOS Sub-μW Ultra-Compact and Low-Effort Design PWM-Based ADC.

Guido Di Patrizio Stanchieri Orazio Aiello Andrea De Marcellis

Published in: ISCAS (2024)

Keyphrases

high speed
single chip
neural network
case study
user interface
circuit design
analog to digital converter
low cost
low power
design process
power consumption
design methodology
cmos technology