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Senju: A Framework for the Design of Highly Parallel FPGA-based Iterative Stencil Loop Accelerators.

Emanuele Del SozzoDavide ConficconiMarco D. SantambrogioKentaro Sano
Published in: FPGA (2023)
Keyphrases
  • highly parallel
  • single chip
  • low power
  • efficient implementation
  • software architecture
  • general purpose
  • fine grained
  • design patterns
  • high speed
  • embedded systems
  • hardware design