A hardware-efficient architecture for multi-resolution motion estimation using fully reconfigurable processing element array.
Xianghu JiChuang ZhuHuizhu JiaXiaodong XieHai Bing YinPublished in: ICME (2011)
Keyphrases
- motion estimation
- hardware implementation
- multiresolution
- reconfigurable hardware
- real time
- low cost
- parallel architecture
- hardware architecture
- systolic array
- hardware software
- processing units
- general purpose processors
- computation intensive
- processing elements
- vlsi implementation
- data processing
- general purpose
- central processor
- dedicated hardware
- parallel execution
- hardware and software
- parallel architectures
- hardware design
- heterogeneous computing
- computer systems
- high speed
- optical flow
- content addressable memory
- programmable logic
- vlsi architecture
- memory management
- software implementation
- hierarchical representation
- embedded systems
- parallel processing
- software architecture
- video sequences
- image processing