Body-bias compensation technique for SubThreshold CMOS static logic gates.
Luiz Alberto Pasini MelekMárcio C. SchneiderCarlos Galup-MontoroPublished in: SBCCI (2004)
Keyphrases
- floating gate
- logic circuits
- delay insensitive
- low voltage
- focal plane
- random access memory
- low power
- human body
- modal logic
- chip design
- logic programming
- classical logic
- low cost
- power consumption
- circuit design
- multi valued
- infrared
- high speed
- defeasible logic
- predicate logic
- variance reduction
- computational properties
- asynchronous circuits
- proof theory
- automated reasoning
- analog vlsi
- image sequences