Low-power design of combinational CMOS networks.
Dmitry I. CheremisinovLiudmila D. CheremisinovaPublished in: EWDTS (2013)
Keyphrases
- low power
- logic circuits
- power consumption
- single chip
- high speed
- low cost
- cmos technology
- low power consumption
- ultra low power
- vlsi architecture
- mixed signal
- digital signal processing
- nm technology
- power dissipation
- vlsi circuits
- gate array
- image sensor
- multi channel
- cmos image sensor
- high power
- power reduction
- delay insensitive
- analog to digital converter
- low voltage
- wireless transmission
- signal processor
- circuit design
- signal processing
- image processing