Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration.
Jian HuangMatthew ParrisJooheung LeeRonald F. DeMaraPublished in: ERSA (2008)
Keyphrases
- pipelined architecture
- hardware implementation
- real time
- scalable distributed
- hardware architecture
- image compression
- dynamic environments
- software implementation
- hardware architectures
- hardware design
- dedicated hardware
- parallel architecture
- discrete cosine transform
- low cost
- management system
- fpga implementation
- software systems
- high speed
- xilinx virtex