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An improved comparison circuit for low power pre-computation-based content-addressable memory designs.
Yu-Ting Pai
Chia-Han Lee
Shanq-Jang Ruan
Edwin Naroska
Published in:
ICECS (2009)
Keyphrases
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low power
high speed
content addressable memory
logic circuits
nm technology
power consumption
low cost
cmos technology
power reduction
gate array
vlsi circuits
power dissipation
single chip
delay insensitive
digital signal processing
mixed signal
low power consumption
vlsi architecture
image sensor
general purpose