A 100 pJ/bit, (32, 8) CMOS Analog Low-Density Parity-Check Decoder Based on Margin Propagation.
Ming GuShantanu ChakrabarttyPublished in: IEEE J. Solid State Circuits (2011)
Keyphrases
- low density parity check
- analog to digital converter
- ldpc codes
- low power
- successive approximation
- vlsi architecture
- channel coding
- source coding
- mixed signal
- error correction
- decoding algorithm
- power consumption
- distributed video coding
- high speed
- error resilience
- low complexity
- low cost
- channel capacity
- message passing
- vlsi implementation
- physical layer
- image transmission
- unequal error protection
- error resilient
- rate allocation
- error propagation
- turbo codes
- video transmission
- error concealment
- image compression