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A 32-b RISC/DSP microprocessor with reduced complexity.
Michael Dolle
Satwinder Jhand
Walter Lehner
Otto Müller
Manfred Schlett
Published in:
IEEE J. Solid State Circuits (1997)
Keyphrases
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reduced complexity
instruction set
vector quantization
digital signal processing
high speed
signal processing
application specific
floating point
low power consumption
computer architecture
low cost
low power
motion estimation algorithm
embedded systems
real time
binary images
image compression
three dimensional