Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs.
Álvaro VázquezFlorent de DinechinPublished in: FPT (2010)
Keyphrases
- efficient implementation
- parallel architectures
- hardware implementation
- highly parallel
- map reduce
- parallel implementation
- efficient processing
- graphics processing units
- parallel processing
- processing elements
- field programmable gate array
- lookup table
- computer architecture
- hardware design
- distributed memory
- low cost
- floating point
- active set