A cost-efficient hardware architecture of deblocking filter in HEVC.
Xin YeDandan DingLu YuPublished in: VCIP (2014)
Keyphrases
- cost efficient
- hardware architecture
- deblocking filter
- video coding standard
- low bit rate
- video compression
- video codec
- motion compensation
- coding method
- video coding
- coding efficiency
- motion compensated
- hardware implementation
- video communication
- discrete cosine transform
- blocking artifacts
- motion vectors
- intra prediction
- low power
- digital video
- block size
- macroblock
- low complexity
- motion estimation
- bit rate
- video streaming
- image coding
- image quality
- rate distortion
- field programmable gate array
- inter frame
- delay insensitive
- transform domain
- associative memory
- spatial domain
- visual quality
- video conferencing
- image compression
- coding scheme
- block matching
- real time
- higher quality
- bitstream
- power consumption
- neural network