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A FPGA HardWare Architecture for AZSPWM Based on a Taylor Series Decomposition.
Andrea Donisi
Luigi Di Benedetto
Rosalba Liguori
Gian Domenico Licciardo
Alfredo Rubino
Published in:
ApplePies (2022)
Keyphrases
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hardware architecture
taylor series
hardware implementation
field programmable gate array
hardware architectures
xilinx virtex
numerical integration
associative memory
pattern recognition
machine learning
image processing
video sequences
high speed
partial differential equations
ordinary differential equations