RTL implementations and FPGA benchmarking of selected CAESAR Round Two authenticated ciphers.

William Diehl Kris Gaj

Published in: Microprocess. Microsystems (2017)

Keyphrases

software implementation
hardware architectures
high speed
low cost
block cipher
hardware architecture
signal processing
efficient implementation
hardware implementation
randomly selected
authentication scheme
real time image processing
key exchange protocol
data acquisition
single chip
computer systems
real time