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A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter.
Alfio Zanchi
Frank (Ching-Yuh) Tsay
Published in:
IEEE J. Solid State Circuits (2005)
Keyphrases
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mixed signal
analog to digital converter
signal to noise ratio
multi channel
feature selection
database
noise reduction
dual channel
image processing
sampling rate
absolute difference
processing pipeline