A novel low power 8T SRAM cell design using lower and upper self controllable voltage level techniques in 45 nm technology.
Prashant UpadhyayRajib KarDurbadal MandalSakti Prasad GhoshalPublished in: Int. J. Comput. Aided Eng. Technol. (2016)
Keyphrases
- low power
- nm technology
- power consumption
- single chip
- low cost
- power dissipation
- high speed
- low power consumption
- vlsi architecture
- logic circuits
- digital signal processing
- cmos technology
- mixed signal
- power reduction
- energy dissipation
- gate array
- power saving
- wireless transmission
- high power
- vlsi circuits
- ultra low power
- low voltage
- embedded systems
- object oriented
- pattern recognition
- real time