An efficient hardware architecture for interpolation filter of HEVC decoder.
Manel KammounAhmed Ben AtitallahNouri MasmoudiPublished in: SSD (2015)
Keyphrases
- hardware architecture
- interpolation filter
- video codec
- motion compensation
- motion compensated
- video coding standard
- video coding
- low complexity
- hardware implementation
- video compression
- motion estimation
- motion vectors
- field programmable gate array
- motion compensated prediction
- associative memory
- rate distortion
- frequency domain
- computationally efficient
- image interpolation
- computer systems
- signal processing
- neural network