A 1 GSa/s, Reconfigurable Soft-core FPGA ADC (Abstract Only).
Stefan VisserHarald HomulleEdoardo CharbonPublished in: FPGA (2016)
Keyphrases
- field programmable gate array
- hardware implementation
- low cost
- digital signal
- systolic array
- reconfigurable architecture
- real time
- reconfigurable hardware
- embedded systems
- high speed
- fpga implementation
- image processing algorithms
- parallel computing
- high level
- power reduction
- parallel architecture
- hardware architecture
- hardware design
- gravitational search algorithm
- software implementation
- single chip
- signal processing
- neural network
- real time image processing
- low power consumption
- low power
- efficient implementation
- parallel processing