Segment-Parallel Predictor for FPGA-Based Hardware Compressor and Decompressor of Floating-Point Data Streams to Enhance Memory I/O Bandwidth.
Kentaro SanoKazuya KatahiraSatoru YamamotoPublished in: DCC (2010)
Keyphrases
- floating point
- floating point arithmetic
- memory bandwidth
- data streams
- instruction set
- parallel hardware
- level parallelism
- main memory
- graphics processing units
- processing elements
- fixed point
- internal memory
- hardware architecture
- incoming data
- virtual memory
- ibm power processor
- application specific
- computational power
- sparse matrices
- external memory
- high bandwidth
- hardware implementation
- data transfer
- gigabit ethernet
- hardware and software
- memory access
- hardware design
- computing power
- massively parallel
- floating point unit
- cache misses
- commodity hardware
- field programmable gate array
- parallel processing
- general purpose
- low cost
- memory requirements
- database systems