Hardware architectures for successive cancellation decoding of polar codes.
Camille LerouxIdo TalAlexander VardyWarren J. GrossPublished in: ICASSP (2011)
Keyphrases
- hardware architectures
- decoding algorithm
- parity check
- error control
- reed solomon
- ldpc codes
- low density parity check
- joint source channel
- computational power
- hardware architecture
- error correcting
- error correction
- decoding complexity
- rotation invariant
- turbo codes
- decoding process
- reed solomon codes
- polar coordinates
- fourier transform
- zernike moments
- graphical models
- image transmission
- frequency domain
- computer systems
- rate allocation
- coding scheme
- parallel processing
- soft decision
- hardware implementation