A Self-Timed Pipeline Circuit for Low-Power Surrounding LSI Chips.
Shuji SannomiyaKazuhiro KomatsuMakoto IwataPublished in: PDPTA (2007)
Keyphrases
- low power
- high speed
- latent semantic indexing
- logic circuits
- cmos technology
- power reduction
- single chip
- gate array
- power dissipation
- vlsi architecture
- high power
- vlsi circuits
- delay insensitive
- wireless transmission
- low power consumption
- real time
- digital signal processing
- chip design
- power consumption
- mixed signal
- nm technology
- low cost
- frame rate
- low complexity
- signal to noise ratio